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AS7C33512PFD18A - 3.3V 512K x 18 pipeline burst synchronous SRAM

AS7C33512PFD18A Description

November 2004 ® AS7C33512PFD18A 3.3V 512K × 18 pipeline burst synchronous SRAM .
The AS7C33512PFD18A is a high performance CMOS 8-Mbit Synchronous Static Random Access Memory (SRAM) devices organized as 524,288 words × 18 bits and.

AS7C33512PFD18A Features

* Organization: 524,288 words × 18 bits
* Fast clock speeds to 166 MHz
* Fast clock to data access: 3.5/4.0 ns
* Fast OE access time: 3.5/4.0 ns
* Fully synchronous register-to-register operation
* Dual-cycle deselect
* Asynchronous output enab

AS7C33512PFD18A Applications

* Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate i

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3.3V 512K pipeline burst synchronous SRAM Alliance Semiconductor Corporation
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