Description
January 2001 Preliminary Information ® AS7C3364PFS32A AS7C3364PFS36A 3.3V 64K X 32/36 pipeline burst synchronous SRAM .
The AS7C3364PFS32A and AS7C3364PFS36A are high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 65,536 word.
Features
* Organization: 65,536 words × 32 or 36 bits
* Fast clock speeds to 166 MHz in LVTTL/LVCMOS
* Fast clock to data access: 3.5/3.8/4.0/5.0 ns
* Fast OE access time: 3.5/3.8/4.0/5.0 ns
* Fully synchronous register-to-register operation
* Single register “
Applications
* Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/ 36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting BWE and the appropria
