* Fast clock rate: 200MHz
* Differential Clock CK & CK
* Bi-directional DQS
* DLL enable/disable by EMRS
* Fully synchronous operation
* Internal pipeline architecture
* Four internal banks, 4M x 16-bit for each bank
* Programmable Mode
AS4C16M16D1A Datasheet (2.01 MB)
AS4C16M16D1A
Alliance Semiconductor
2.01 MB
16m x 16 ddr1.
16Mx16 DDR1-AS4C16M16D1A
Revision History AS4C16M16D1A - 66-pin TSOPII PACKAGE
Revision Details Rev 1.1 Preliminary datasheet
Date July 2015
Allian.
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