AS4C16M16S Datasheet - Alliance Semiconductor

AS4C16M16S 16M x 16 bit Synchronous DRAM

Confidential 3 Rev. 3 Feb. /2014 Row Decoder ~ AS4C16M16S Table 3. Pin Details Symbol CLK Type Input Description Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output regis.

AS4C16M16S Features

* Fast access time from clock: 5.4/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 4M word x 16-bit x 4-bank Programmable Mode registers - CAS Latency: 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop

AS4C16M16S-AllianceSemiconductor.pdf