AS4C1G8D3LA Datasheet - Alliance Semiconductor

8Gbit DDR3L SDRAM

Revision History 8Gbit DDR3L SDRAM 8 BANKS X 128Mbit X 8 - Dual Die Package (DDP) 78ball FBGA Package Revision Details Rev 1.0 Preliminary datasheet AS4C1G8D3LA Date Feb. 2019 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 41 - Rev.1.0. Feb.2019 AS4C1G8D3LA Specifications - Density : 8G bits - Organization : - 128M words x 8 bits.

8Gbit DDR3L SDRAM

AS4C1G8D3LA Features

* - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipe- lined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver - DQS is edge-a

AS4C1G8D3LA General Description

Pin CK, CK CKE CS ODT RAS, CAS, WE DM BA0 - BA2 A0 - A15 A10 / AP A12 / BC RESET DQ DQS, DQS NC Type Input Input Input Input Input Input Input Input Input Input Input Input/ Output Input/ Output Function Clock : CK and CK are differential clock inputs. All address and control input signals are sa.

AS4C1G8D3LA Datasheet (2.14 MB)