* Fast clock rate: 200MHz
* Differential Clock CK & CK
* Bi-directional DQS
* DLL enable/disable by EMRS
* Fully synchronous operation
* Internal pipeline architecture
* Four internal banks, 8M x 16-bit for each bank
* Programmable Mode and Extended Mode registers - C
AS4C32M16D1 Datasheet (1.09 MB)
AS4C32M16D1
Alliance Semiconductor
1.09 MB
32m x 16 bit ddr synchronous dram.
AS4C32M16D1
Revision History
AS4C32M16D1 - 60-Ball, 8x13x1.2 mm (max) TFBGA PACKAGE
Revision Details Rev 1.0 Preliminary datasheet
Date August 201.
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