* - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipe- lined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver - DQS is edge-a
AS4C512M16D3LA Datasheet (1.92 MB)
AS4C512M16D3LA
Alliance Semiconductor
1.92 MB
8gbit ddr3l sdram.
Revision History 8Gbit DDR3L SDRAM
8 BANKS X 64Mbit X 16 - Dual Die Package (DDP) 96ball FBGA Package
Revision Details Rev 1.0 Preliminary datasheet
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