* 25 MIPS, 40 ns Maximum Instruction Rate Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data (Three-Bus Performance) Dual Data Address Generators with Modulo and Bit-Reverse Addressing Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycl
ADSP-2115 Datasheet (460.54 KB)
ADSP-2115
460.54 KB
Dsp microcomputers.
a
ADSP-2100 Family DSP Microcomputers
ADSP-21xx
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture fo.
📁 Related Datasheet
ADSP-2111 - DSP Microcomputers
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a
ADSP-2100 Family DSP Microputers
ADSP-21xx
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture fo.
ADSP-21160 - DSP Microcomputer
(Analog Devices)
a
Preliminary Technical Data
SUMMARY
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DSP Microputer ADSP-21160
KEY FEATURES
• • • • • • •
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High performance 32-bit DSP—applications .
ADSP-21160M - Digital Signal Processor
(Analog Devices)
SUMMARY
High performance 32-bit DSP—applications in audio, medical, military, graphics, imaging, and munication
Super Harvard architecture—4 indepe.
ADSP-21160N - Digital Signal Processor
(Analog Devices)
SUMMARY
High performance 32-bit DSP—applications in audio, medical, military, graphics, imaging, and munication
Super Harvard architecture—4 indepe.
ADSP-21161 - SHARC Processor Hardware Reference
(Analog Devices)
ADSP-21161 SHARC® Processor Hardware Reference
Revision 4.0, February 2005 Part Number 82-001944-01
Analog Devices, Inc. One Technology Way Norwood,.
ADSP-21161N - SHARC Processor
(Analog Devices)
SUMMARY
High performance 32-Bit DSP—applications in audio, medical, military, wireless munications, graphics, imaging, motor-control, and telephony.
ADSP-2100A - DSP Microcomputers
(Analog Devices)
a
DSP Microputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
ADSP-2101 - DSP Microcomputers
(Analog Devices)
a
ADSP-2100 Family DSP Microputers
ADSP-21xx
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture fo.
