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ADSP-21060 - SHARC Processor

ADSP-21060 Description

SHARC Processor ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC SUMMARY High performance signal processor for communications, g.
4 SHARC Family Core Architecture 4 Memory and I/O Interface Features 5 Development Tools 8 Evaluation Kit 9 Designing an Emulator-Compatible DSP.

ADSP-21060 Features

* 240-lead thermally enhanced MQFP_PQ4 package, 225-ball plastic ball grid array (PBGA), 240-lead hermetic CQFP package RoHS compliant packages KEY FEATURES
* PROCESSOR CORE 40 MIPS, 25 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Dual

ADSP-21060 Applications

* Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units
* multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals
* a complete system-on-a-chip Integrated multipr

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SHARC Processor ANALOG DEVICES
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