* 25 MIPS, 40 ns Maximum Instruction Rate (5 V) Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data (Three-Bus Performance) Dual Data Address Generators with Modulo and Bit-Reverse Addressing Efficient Program Sequencing with Zero-Overhead Looping: Singl
ADSP-2100A Datasheet (243.08 KB)
ADSP-2100A
243.08 KB
Dsp microcomputers.
a
DSP Microcomputers with ROM
ADSP-216x
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-.
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FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns,.
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SHARC Processor
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High performance signal processor for munications, g.
ADSP-21060L - SHARC Processor
(ANALOG DEVICES)
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