ADSP-21020 Datasheet - Analog Devices

ADSP-21020, 32/40-Bit IEEE Floating-Point DSP Microprocessor

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32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FUNCTIONAL BLOCK DIAGRAM DATA ADDRESS GENERATORS DAG 1 DAG 2 INSTRUCTION CACHE PROGRAM SE.

Features

* Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution 100 MFLOPS Peak, 66 MFLOPS Sustained Performance 1024-Point Complex FFT Benchmark: 0.58 ms Divide (y/x): 180 ns Inverse Square Roo

Applications

* Its architecture is similar to that of Analog Devices’ ADSP-2100 family of fixed-point DSP processors. Fabricated in a high-speed, low-power CMOS process, the ADSP-21020 has a 30 ns instruction cycle time. With a highperformance on-chip instruction cache, the ADSP-21020 can execute every instructio

ADSP-21020_AnalogDevices.pdf