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ADSP-21061L, ADSP-21061 Commercial Grade SHARC DSP Microcomputer

ADSP-21061L Description

a SUMMARY High performance signal processor for communications, graphics, and imaging applications Super Harvard Architecture Four independent buses f.
3 SHARC Family Core Architecture 3 Memory and I/O Interface Features 4 Porting Code From the ADSP-21060 or ADSP-21062 7 Development Tools 7 Addit.

ADSP-21061L Features

* KEY FEATURES
* PROCESSOR CORE 50 MIPS, 20 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Commercial Grade SHARC DSP Microcomputer ADSP-21061/ADSP-21061L Dual data address generators with modulo and bit-reverse addressing Efficient prog

ADSP-21061L Applications

* Super Harvard Architecture Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units
* multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals
* a complete system-on-a-chip Integrated mult

📥 Download Datasheet

This datasheet PDF includes multiple part numbers: ADSP-21061L, ADSP-21061. Please refer to the document for exact specifications by model.
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Datasheet Details

Part number
ADSP-21061L, ADSP-21061
Manufacturer
Analog Devices ↗
File Size
865.10 KB
Datasheet
ADSP-21061-AnalogDevices.pdf
Description
Commercial Grade SHARC DSP Microcomputer
Note
This datasheet PDF includes multiple part numbers: ADSP-21061L, ADSP-21061.
Please refer to the document for exact specifications by model.

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Commercial Grade SHARC DSP Microcomputer Analog Devices
Analog Devices ADSP-21061L-like datasheet