Description
SUMMARY High performance 32-bit DSP *applications in audio, medical, military, graphics, imaging, and communication Super Harvard architecture<.
4 ADSP-21160x Family Core Architecture 4 Memory and I/O Interface Features 7 Development Tools 9 Additional Information 10 Related Signal Chains.
Features
* and ports (serial, link, external bus, and JTAG)
SHARC
Digital Signal Processor
ADSP-21160M/ADSP-21160N
FEATURES
100 MHz (10 ns) core instruction rate (ADSP-21160N) Single-cycle instruction execution, including SIMD opera-
tions in both computational units Dual data address generators (DAGs) with
Applications
* in audio, medical, military, graphics, imaging, and communication
Super Harvard architecture
* 4 independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I/O
Backward compatible
* assembly source level compatible with code for ADSP-2106x DSPs
Single-instr
