ADSP-21160N, ADSP-21160M Datasheet (Analog Devices)

ADSP-21160N, ADSP-21160M, Digital Signal Processor

SUMMARY High performance 32-bit DSP applications in audio, medical, military, graphics, imaging, and communication Super Harvard architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I/O Backward compatible assembly source level compatible with code for ADSP-2106x DSPs Single-instruction, multiple-data (SIMD) computational architecture two 32-bit IEEE floating-point computation units, each with a multiplier, ALU,

ADSP-21160N Features

* and ports (serial, link, external bus, and JTAG) SHARC Digital Signal Processor ADSP-21160M/ADSP-21160N FEATURES 100 MHz (10 ns) core instruction rate (ADSP-21160N) Single-cycle instruction execution, including SIMD opera- tions in both computational units Dual data address generators (DAGs) with