ADSP-21161N - SHARC Processor
SUMMARY High performance 32-Bit DSP applications in audio, medical, military, wireless communications, graphics, imaging, motor-control, and telephony Super Harvard Architecture four independent buses for dual data fetch, instruction fetch, and nonintrusive zerooverhead I/O Code compatible with all other sharc family DSPs Single-instruction multiple-data (SIMD) computational archi- tecture two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shif
ADSP-21161N Features
* and I/O ports (serial, link, external bus, SPI, and JTAG) ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit floating-point formats 100 MHz/110 MHz core instruction
