Description
SHARC Processors ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SUMMARY High performance 32-bit/40-bit floating point processor optimized for.
3
SHARC Family Core Architecture 4 Family Peripheral Architecture 6 I/O Processor Features 8 System Design 8 Development Tools 9 Additional Info.
Features
* include:
JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit
access under program control to sensitive code PLL has a wide variety of software and hardware multi-
plier/divider ratios Available in 136-ball CSP_BGA and 144-lead LQFP_EP
packages
SI
Applications
* interface, S/PDIF transceiver, DTCP (digital transmission content protection protocol), serial ports, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 56.
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter 8 channels of