ADSP-SC572 Description
SHARC+ Dual-Core DSP with ARM Cortex-A5 ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 SYSTEM .
3
ARM Cortex-A5 Processor 5 SHARC Processor 6 SHARC+ Core Architecture 8 System Infrastructure 10 System Memory Map 11 Security Features 13 Sec.
ADSP-SC572 Features
* Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed
A
ADSP-SC572 Applications
* SYSTEM CONTROL
SECURITY AND PROTECTION SYSTEM PROTECTION (SPU)
SYSTEM MEMORY PROTECTION UNIT (SMPU)
FAULT MANAGEMENT ARM® TrustZone® SECURITY
DUAL CRC WATCHDOGS OTP MEMORY THERMAL MONITOR UNIT (TMU)
PROGRAM FLOW SYS EVENT CORE 0 (GIC) SYS EVENT CORES 1-2 (SEC) TRIGGER ROUTING (TRU)
CLOCK, RESET, AN
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