Description
a .
Features
* 38 ns Instruction Cycle Time (26 MIPS) from 13.00 MHz Crystal ADSP-2100 Family Code and Function Compatible with New Instruction Set Enhanced for Bit Manipulation Instructions, Multiplication Instructions, Biased Rounding, and Global Interrupt Masking 2K ؋ 24 Words of On-Chip Program Memory RAM 2K ؋Applications
* such as Speech Compression, Speech Processing, Speech Recognition, Text-to Speech, and Speech-to-Text conversion. The ADSP-21msp58/59 combines the ADSP-2100 base architecture (three computation units, data address generators, and program sequencer) with two serial ports, a host interface port, an anADSP21msp59 Distributors
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