ADSP-SC583 Description
SHARC+ Dual-Core DSP with Arm Cortex-A5 ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587 SYSTEM .
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Arm Cortex-A5 Processor 5 SHARC Processor 6 SHARC+ Core Architecture 8 System Infrastructure 10 System Memory Map 11 Security Features 14 Sec.
ADSP-SC583 Features
* Dual enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short-word, word, long-word a
ADSP-SC583 Applications
* SYSTEM CONTROL
SECURITY AND PROTECTION SYSTEM PROTECTION (SPU)
SYSTEM MEMORY PROTECTION UNIT (SMPU)
FAULT MANAGEMENT Arm® TrustZone® SECURITY
DUAL CRC WATCHDOGS OTP MEMORY THERMAL MONITOR UNIT (TMU)
PROGRAM FLOW SYS EVENT CORE 0 (GIC) SYS EVENT CORES 1-2 (SEC) TRIGGER ROUTING (TRU)
CLOCK, RESET, AN
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