AS4DDR264M72PBG Datasheet (Austin Semiconductor) - 64Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

AS4DDR264M72PBG, 64Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

On-Die-Termination: Registered High enables on data bus termination Differential input clocks, one set for each x16bits A7, A8, A9, A10, B7, Ax Input B8, B9, B10, C7, C8, C9, C10, D7 D8, D9, D10 DNU Future Input E8, E9m D9 BA0, BA1, BA2 Input A2, A3, A4, A13, A14, DQx Input/Output A15, B1, B2, B3,

AS4DDR264M72PBG Features

* DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package:

* 255 Plastic Ball Grid Array (PBGA), 25 x 32mm

* 1.27mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n