AS4DDR264M72PBG1 - 4.8 Gb SDRAM-DDR2

Micross

Datasheet Details

DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package:.
Proprietary Enchanced Die Stacked iPEM.
208 Plastic Ball Grid Array (PBGA), 16 x 23mm.
1.00mm ball pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eight internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst l.

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Published: Jan 8, 2017 |