Description
i PEM 4.8 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc.AS4DDR264M72PBG1 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microc.
On-Die-Termination: Registered High enables on data bus termination Differential input clocks, one set for each x16bits Clock enable which activates a.
Features
* DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package:
* Proprietary Enchanced Die Stacked iPEM
* 208 Plastic Ball Grid Array (PBGA), 16 x 23mm
* 1.00mm ball pitch Differential data strobe (DQS, DQS#) per byte
Applications
* Upgradable to 128M x 72 density in future Pin/Function equivalent to White W3H64M72E-xBSx
* ConfigurationAddressing Parameter Configuration RefreshC
