AS4DDR264M72PBG1 Datasheet (Austin Semiconductor) - 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit

AS4DDR264M72PBG1, 64Mx72 DDR2 SDRAM w/ SHARED CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit

On-Die-Termination: Registered High enables on data bus termination Differential input clocks, one set for each x16bits Clock enable which activates all on silicon clocking circuitry Chip Selects, one for each 16 bits of the data bus width Command input which along with CAS, WE and CS define operati

AS4DDR264M72PBG1 Features

* DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package:

* Proprietary Enchanced Die Stacked iPEM

* 208 Plastic Ball Grid Array (PBGA), 16 x 23mm

* 1.00mm ball pitch Differential data strobe (DQS, DQS#) per byte