MT4C4001J Datasheet - Austin Semiconductor

MT4C4001J 1 MEG x 4 DRAM Fast Page Mode DRAM

The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the first 10 bits and CAS the la.

MT4C4001J Features

* Industry standard x4 pinout, timing, functions, and packages

* High-performance, CMOS silicon-gate process

* Single +5V±10% power supply

* Low-power, 2.5mW standby; 300mW active, typical

* All inputs, outputs, and clocks are fully TTL and CMOS compatible

MT4C4001J Datasheet (276.87 KB)