AP2302 Datasheet (BCD Semiconductor) - 3A DDR TERMINATION REGULATOR

AP2302, 3A DDR TERMINATION REGULATOR

The AP2302 linear regulator is designed to meet the JEDEC specification SSTL-2 and SSTL-18 for termination of DDR-SDRAM.

The regulator can sink or source up to 3A current continuously, offers enough current for most DDR applications.

Output voltage is designed to track the reference voltage within a

AP2302 Features

* Support Both DDR I (1.25VTT) and DDR II (0.9VTT) Requirements Source and Sink Current up to 3A High Accuracy Output Voltage at Full-load Adjustable VOUT by External Resistors Shutdown for Standby or Suspend Operation with High-impedance Output Mode Applications