CY28343 Datasheet - Cypress Semiconductor

CY28343 Zero Delay SDR/DDR Clock Buffer

2, 3] Pin 10 47 23 30,32,36,38 42,44 29,31,35,37 41,43 2-5,8,9 15-18,21 46 Name CLKIN FBIN_DDR FBIN_SDR DDRT(0:5) DDRC(0:5) SDRAM(0:12) FBOUT_DDR I/O I I PD I PD O O O O Clock Input. Reference the PLL Feedback Clock Output. Connect to FBOUT_DDR for accessing the PLL. See Function Table on page 1 Fee.

CY28343 Features

* Phase-lock loop clock distribution for DDR and SDR SDRAM applications

* One-single-end clock input to 6 pairs DDR outputs or 13 SDR outputs.

* External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for SDR. Table 1. Function Table S

CY28343_CypressSemiconductor.pdf