CY2DP818 Datasheet - Cypress Semiconductor

1:8 Clock Fanout Buffer

* Low-voltage operation VDD = 3.3 V

* 1:8 fanout

* Operation to350 MHz

* Single input configurable for LVDS, LVPECL, or LVTTL

* 8 pair of LVPECL outputs

* Drives a 50 ohm load

* Low input capacitance

* Low output skew

* Low propagation delay (tpd = 4 ns, typical)

CY2DP818

Cypress Semiconductor

319.29 KB

1:8 clock fanout buffer.

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CY2DP818 Clock Fanout Buffer Cypress Semiconductor

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