CY2SSTV855 Datasheet (Cypress Semiconductor) - Differential Clock Buffer/Driver

CY2SSTV855, Differential Clock Buffer/Driver

The CY2SSTV855 is a high-performance, very-low-skew, very-low-jitter zero-delay buffer that distributes a differential clock input pair (SSTL_2) to four differential (SSTL_2) pairs of clock outputs and one differential pair of feedback clock outputs.

In support of low power requirements, when power-

CY2SSTV855 Features

* Phase-locked loop (PLL) clock distribution for Double Data Rate Synchronous DRAM applications

* 1:5 differential outputs

* External feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input

* SSCG: Spread Aware™ for electromagnetic interfer