CY2XP306 Datasheet - Cypress Semiconductor

CY2XP306 - High-frequency Programmable PECL Clock Generation Module

CY2XP306 PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table No Connect SER_DATA Serial Interface Data SER_CLK

CY2XP306 Features

* 60 ps typical Cycle-to-Cycle Jitter

* 30 ps typical Output-Output Skew

* Phase-locked loop (PLL) multiplier select

* LVTTL or XO Input; Six LVPECL Outputs

* Selectable Output Divider (/2)

* 1

* 133 MHz Input Frequency Range

* 62.5

CY2XP306_CypressSemiconductor.pdf