CY2XP306 - High-frequency Programmable PECL Clock Generation Module

Cypress Semiconductor

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Datasheet Details

Part number	CY2XP306
Manufacturer	Cypress Semiconductor
File Size	235.76 KB
Description	High-frequency Programmable PECL Clock Generation Module
Datasheet	CY2XP306_CypressSemiconductor.pdf

CY2XP306 Product details

Description

CY2XP306 PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table No Connect SER_DATA Serial Interface Data SER_CLK Serial Interface Clock Example PLL Output Frequency 311.04 MHz 312.5 MHz 155.52 MHz 156.25 MHz 311.04 MHz Table 2. Output Frequency Table Control Pin FSELA FSELB Table 3. Function Table Control Pin

Features

60 ps typical Cycle-to-Cycle Jitter.
30 ps typical Output-Output Skew.
Phase-locked loop (PLL) multiplier select.
LVTTL or XO Input; Six LVPECL Outputs.
Selectable Output Divider (/2).
1.
133 MHz Input Frequency Range.
62.5.
500 MHz Output Frequency Range.
36-pin VFBGA, 6 × 8 × 1 mm.
3.3V operation.
Serially Configurable Multiply Ratios Block Diagram QA1 FSELA QA1# PLL_MULT 0 1 QA2 QA2# Q.

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Published: Jul 30, 2011 |