CY7C1412JV18 - SRAM 2-Word Burst Architecture

Product Overview

Cypress Semiconductor

Part number	CY7C1412JV18
Manufacturer	Cypress Semiconductor
File Size	682.68 KB
Description	SRAM 2-Word Burst Architecture
Datasheet	CY7C1412JV18 Datasheet
Additional preview pages of the CY7C1412JV18 datasheet.

The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and CY7C1414JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.

Configurations CY7C1410JV18.
4M x 8 CY7C1425JV18.
4M x 9 CY7C1412JV18.
2M x 18 CY7C1414JV18.
1M x 36 Separate independent read and write data ports.
Supports concurrent transactions 267 MHz clock for high bandwidth 2-word burst on all accesses (data transferred at 534 MHz) at 267 MHz.
Double Data Rate (DDR) interfaces on both read and write ports www. DataSheet4U. com.
Functional.

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Published: Jul 23, 2008 |