CY7C1412KV18 Datasheet 36-mbit Qdr Ii Sram Two-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1425KV18 CY7C1412KV18 CY7C1414KV18 36-Mbit QDR® II SRAM Two-Word Burst Architecture 36-Mbit QDR® II SRAM Two-Word Burst.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	CY7C1412KV18
Manufacturer	Cypress (now Infineon)
File Size	1.26 MB
Description	36-Mbit QDR II SRAM Two-Word Burst Architecture
Datasheet	CY7C1412KV18 CY7C1425KV18 Datasheet (PDF)

Separate independent read and write data ports.
Supports concurrent transactions.
333 MHz clock for high bandwidth.
Two-word burst on all accesses.
Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) sim.

Part Number	Description
CY7C1412AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1412JV18	SRAM 2-Word Burst Architecture
CY7C1412V18	SRAM 2-Word Burst Architecture
CY7C141	1K x 8 Dual-Port Static RAM
CY7C1410AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1410JV18	(CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C1410V18	(CY7C14xxV18) SRAM 2-Word Burst Architecture
CY7C1411AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411BV18	(CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18	(CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture