CY7C1412JV18 Description
QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations.
CY7C1412JV18 Key Features
- 4M x 8 CY7C1425JV18
- 4M x 9 CY7C1412JV18
- 2M x 18 CY7C1414JV18
- 1M x 36
- Supports concurrent transactions 267 MHz clock for high bandwidth 2-word burst on all accesses (data transferred at 534
- Double Data Rate (DDR) interfaces on both read and write ports
- Functional Description