CY7C371
Cypress Semiconductor
566.19kb
32-macrocell flash cpld. D D D D D 32 macrocells in two logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins No hidden delays High speed Ċ fM
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CY7C371I - UltraLogic 32-Macrocell Flash CPLD
(Cypress Semiconductor)
USE ULTRA37000™ FOR ALL NEW DESIGNS
CY7C371i
UltraLogic™ 32-Macrocell Flash CPLD
Features
• • • • • • • 32 macrocells in two logic blocks 32 I/O pin.
CY7C372I - UltraLogic 64-Macrocell Flash CPLD
(Cypress Semiconductor)
USE ULTRA37000™ FOR ALL NEW DESIGNS
CY7C372i
UltraLogic™ 64-Macrocell Flash CPLD
Features
• 64 macrocells in four logic blocks • 32 I/O pins • Five .
CY7C374 - 128-Macrocell Flash CPLD
(Cypress Semiconductor)
For new designs see CY7C374i
CY7C374
UltraLogic™ 128-Macrocell Flash CPLD
Features
• • • • • • 128 macrocells in eight logic blocks 64 I/O pins 6 de.
CY7C374I - 128-Macrocell Flash CPLD
(Cypress Semiconductor)
74i
CY7C374i
UltraLogic™ 128-Macrocell Flash CPLD
Features
• • • • 128 macrocells in eight logic blocks 64 I/O pins 5 dedicated inputs including 4 c.
CY7C375 - 128-Macrocell Flash CPLD
(Cypress Semiconductor)
7C375: Thursday, September 24, 1992 Revision: October 14, 1995
CY7C375
tUltraLogic 128ĆMacrocell Flash CPLD
Features
D 128 macrocells in eight logi.
CY7C375I - UltraLogic 128-Macrocell Flash CPLD
(Cypress Semiconductor)
USE ULTRA37000™ FOR ALL NEW DESIGNS
CY7C375i
UltraLogic™ 128-Macrocell Flash CPLD
Features
• 128 macrocells in eight logic blocks • 128 I/O pins • F.
CY7C325 - Timing Control Unit
(Cypress)
.
CY7C331 - Asynchronous Registered EPLD
(Cypress Semiconductor)
1CY7C331
fax id: 6016
CY7C331
..
Asynchronous Registered EPLD
Features
• Twelve I/O macrocells each having: — One state flip-flop wi.
CY7C335 - Universal Synchronous EPLD
(Cypress Semiconductor)
1CY 7C33 5
fax id: 6018
CY7C335
..
Universal Synchronous EPLD
Features
• 100-MHz output registered operation • Twelve I/O macrocel.
CY7C340 - Multiple Array Matrix High-Density EPLDs
(Cypress)
E PL D
CY7C340 EPLD Family
Multiple Array Matrix High-Density EPLDs
Features
• Erasable, user-configurable CMOS EPLDs capable of implementing high-.
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