GVT71256ZC36 Datasheet (Cypress Semiconductor) - (GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture

GVT71256ZC36, (GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture

The CY7C1354A/GVT71256ZC36 and CY7C1356A/ GVT71512ZC18 SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa.

These SRAMs are optimized for 100% bus utilization and achieve Zero Bus Latency (ZBL)/No Bus Latency (NoBL).

They integrate 262,144 × 36 and 524

GVT71256ZC36 Features

* Zero Bus Latency, no dead cycles between Write and Read cycles

* Fast clock speed: 200, 166, 133, 100 MHz

* Fast access time: 3.2, 3.6, 4.2, 5.0 ns

* Internally synchronized registered outputs eliminate the need to control OE

* Single 3.3V

* 5% and +5