Description
( DataSheet : www.DataSheet4U.com ) CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture .
The CY7C1354A/GVT71256ZC36 and CY7C1356A/ GVT71512ZC18 SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa.
Features
* Zero Bus Latency, no dead cycles between Write and Read cycles
* Fast clock speed: 200, 166, 133, 100 MHz
* Fast access time: 3.2, 3.6, 4.2, 5.0 ns
* Internally synchronized registered outputs eliminate the need to control OE
* Single 3.3V
* 5% and +5
Applications
* Interleaved or linear four-word burst capability
* Individual byte Write (BWa
* BWd) control (may be tied LOW)
* CEN pin to enable clock and suspend operations
* Three chip enables for simple depth expansion
