Description
( DataSheet : www.DataSheet4U.com ) 1CY7C1357A PRELIMINARY CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 Flow-Thru SRAM with NoBL™.
The CY7C1355A/GVT71256ZB36 and CY7C1357A/ GVT71512ZB18 SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa.
Features
* Zero Bus Latency, no dead cycles between write and read cycles
* Fast clock speed: 133, 117, and 100 MHz
* Fast access time: 6.5, 7.0, 7.5, and 8.0 ns
* Internally synchronized registered outputs eliminate the need to control OE
* Single 3.3V
* 5% and
Applications
* Interleaved or linear 4-word burst capability
* Individual byte write (BWa
* BWd) control (may be tied LOW)
* CKE pin to enable clock and suspend operations
* Three chip enables for simple depth expansion
* SNOOZE MODE for low power standby
* J
