Description
( DataSheet : www.DataSheet4U.com ) 327 CY7C1359A/GVT71256T18 256K x 18 Synchronous-Pipelined Cache Tag RAM .
The Cypress Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal techn.
Features
* Fast match times: 3.5, 3.8, 4.0 and 4.5 ns Fast clock speed: 166, 150, 133, and 100 MHz Fast OE access times:
Applications
* Low-profile JEDEC standard 100-pin TQFP package All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Bur
