CY2DP818 - 1:8 Clock Fanout Buffer

Cypress Semiconductor

Datasheet Details

The Cypress CY2DP818 fanout buffer

Low-voltage operation VDD = 3.3 V.
1:8 fanout.
Operation to350 MHz.
Single input configurable for LVDS, LVPECL, or LVTTL.
8 pair of LVPECL outputs.
Drives a 50 ohm load.
Low input capacitance.
Low output skew.
Low propagation delay (tpd = 4 ns, typical).
Industrial temperature range.
38-pin TSSOP Package Logic Block Diagram INPUT (LVPECL / LVDS / LVTTL) INPUT A INPUT B InConfig.

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Published: Nov 29, 2005 |