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GVT71256ZC36 - (GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture

Cypress Semiconductor

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Datasheet Details

Part number	GVT71256ZC36
Manufacturer	Cypress Semiconductor
File Size	597.12 KB
Description	(GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture
Datasheet	GVT71256ZC36_CypressSemiconductor.pdf

GVT71256ZC36 Product details

Description

The CY7C1354A/GVT71256ZC36 and CY7C1356A/ GVT71512ZC18 SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa.

Features

Zero Bus Latency, no dead cycles between Write and Read cycles.
Fast clock speed: 200, 166, 133, 100 MHz.
Fast access time: 3.2, 3.6, 4.2, 5.0 ns.
Internally synchronized registered outputs eliminate the need to control OE.
Single 3.3V.
5% and +5% power supply VCC.
Separate VCCQ for 3.3V or 2.5V I/O.
Single WEN (Read/Write) control pin.
Positive clock-edge triggered, address, data, and control signal registers for f.

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Published: Apr 13, 2006 |