DFPMUL Datasheet - Digital Core Design

DFPMUL Floating Point Pipelined Multiplier Unit

PIN clk rst en adatai[31:0] bdatai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing A data bus input B data bus input Output Data bus output Output Overflow flag Output Underflow flag Output Invalid result flag Sp.

DFPMUL www.DataSheet4U.com Floating Point Pipelined Multiplier Unit ver 2.70 OVERVIEW Fully synthesizable, static synchronous design with no internal tri-states The DFPMUL uses the pipelined mathematics algorithm to multiply two arguments. The input numbers format is according to IEEE754 standard. DFPMUL supports single precision real number. Multiply operation was pipelined up to 7 levels. Input data are fed every clock cycle. The first result appears after latency depending on pipeline.

DFPMUL Features

* Full IEEE-754 compliance Single precision real format support Simple interface No programming required 7 levels pipeline Full accuracy and precision Overflow, underflow and invalid operation flags Results available at every clock Fully configurab

DFPMUL_DigitalCoreDesign.pdf