DFPMUL Datasheet - Digital Core Design

DFPMUL, Floating Point Pipelined Multiplier Unit

DFPMUL www.DataSheet4U.com Floating Point Pipelined Multiplier Unit ver 2.70 OVERVIEW * Fully synthesizable, static synchronous design with no in.
PIN clk rst en adatai[31:0] bdatai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system rese.

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DFPMUL_DigitalCoreDesign.pdf

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Datasheet Details

Part number:

DFPMUL

Manufacturer:

Digital Core Design

File Size:

172.83 KB

Description:

Floating Point Pipelined Multiplier Unit

Features

* Full IEEE-754 compliance Single precision real format support Simple interface No programming required 7 levels pipeline Full accuracy and precision Overflow, underflow and invalid operation flags Results available at every clock Fully configurab

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DFPMUL Floating Point Pipelined Multiplier Unit Digital Core Design

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