DFPMUL Floating Point Pipelined Multiplier Unit

Digital Core Design

Description

DFPMUL www.DataSheet4U.com Floating Point Pipelined Multiplier Unit ver 2.70 OVERVIEW * Fully synthesizable, static synchronous design with no in.
PIN clk rst en adatai[31:0] bdatai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system rese.

📥 Download Datasheet

DFPMUL Datasheet Preview — Preview of DFPMUL PDF

Datasheet Specifications

Part number: DFPMUL
Manufacturer: Digital Core Design
File Size: 172.83 KB
Datasheet: DFPMUL_DigitalCoreDesign.pdf
Description: Floating Point Pipelined Multiplier Unit

Features

* Full IEEE-754 compliance Single precision real format support Simple interface No programming required 7 levels pipeline Full accuracy and precision Overflow, underflow and invalid operation flags Results available at every clock Fully configurab

DFPMUL Distributors

📁 Related Datasheet

DFP1000 DFP14 DFP16 DFP2N60 DFP30N06 DFP4N60

📌 All Tags

DFPMUL Floating Point Pipelined Multiplier Unit Digital Core Design

Digital Core Design DFPMUL-like datasheet