DFPADD Datasheet - Digital Core Design

DFPADD Floating Point Pipelined Adder Unit

PIN clk rst en adatai[31:0] bdatai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing A data bus input B data bus input Output Data bus output Output Overflow flag Output Underflow flag Output Invalid result flag Al.

DFPADD www.DataSheet4U.com Floating Point Pipelined Adder Unit ver 2.50 OVERVIEW Fully synthesizable, static synchronous design with no internal tri-states The DFPADD uses the pipelined mathematics algorithm to compute sum of two arguments. The input numbers format is according to IEEE-754 standard. DFPADD supports single precision real number. Add operation was pipelined up to 5 levels. Input data are fed every clock cycle. The first result appears after 5 clock periods latency and next.

DFPADD Features

* Full IEEE-754 compliance Single precision real format support Simple interface No programming required 5 levels pipeline Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurab

DFPADD_DigitalCoreDesign.pdf