DFPDIV Datasheet - Digital Core Design

DFPDIV Floating Point Pipelined Divider Unit

PIN clk rst en adatai[31:0] bdatai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing A data bus input B data bus input Output Data bus output Output Overflow flag Output Underflow flag Output Invalid result flag .

DFPDIV www.DataSheet4U.com Floating Point Pipelined Divider Unit ver 2.15 OVERVIEW Fully synthesizable, static synchronous design with no internal tri-states The DFPDIV uses the pipelined mathematics algorithm to divide two arguments. The input numbers format is according to IEEE754 standard. DFPDIV supports single precision real number. Divide operation was pipelined up to 15 levels. Input data are fed every clock cycle. The first result appears after 15 clock periods latency and next r.

DFPDIV Features

* Full IEEE-754 compliance Single precision real format support Simple interface No programming required 15 levels pipeline Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configura

DFPDIV_DigitalCoreDesign.pdf