DFPDIV Datasheet - Digital Core Design

DFPDIV, Floating Point Pipelined Divider Unit

DFPDIV www.DataSheet4U.com Floating Point Pipelined Divider Unit ver 2.15 OVERVIEW * Fully synthesizable, static synchronous design with no inter.
PIN clk rst en adatai[31:0] bdatai[31:0] datao[31:0] ofo ufo ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system re.

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DFPDIV_DigitalCoreDesign.pdf

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Datasheet Details

Part number:

DFPDIV

Manufacturer:

Digital Core Design

File Size:

170.53 KB

Description:

Floating Point Pipelined Divider Unit

Features

* Full IEEE-754 compliance Single precision real format support Simple interface No programming required 15 levels pipeline Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configura

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DFPDIV Floating Point Pipelined Divider Unit Digital Core Design

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