DFPCOMP Floating Point Comparator Unit

Digital Core Design

Description

DFPCOMP www.DataSheet4U.com Floating Point Comparator Unit ver 2.10 OVERVIEW DELIVERABLES * Source code: VHDL Source Code or/and VERILOG Sour.
PIN clk rst en adatai[31:0] bdatai[31:0] gto eqo lto ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system reset Enab.

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Datasheet Specifications

Part number: DFPCOMP
Manufacturer: Digital Core Design
File Size: 170.88 KB
Datasheet: DFPCOMP_DigitalCoreDesign.pdf
Description: Floating Point Comparator Unit

Features

* Full IEEE-754 compliance Single precision real format support Simple interface No programming required 1 level pipeline Results available at every clock Fully configurable Fully synthesizable, static synchronous design with no internal tri-states Deli

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DFPCOMP Floating Point Comparator Unit Digital Core Design

Digital Core Design DFPCOMP-like datasheet