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DFPCOMP Datasheet - Digital Core Design

DFPCOMP Floating Point Comparator Unit

PIN clk rst en adatai[31:0] bdatai[31:0] gto eqo lto ifo TYPE Input Input Input Input Input DESCRIPTION Global system clock Global system reset Enable computing A data bus input B data bus input output A>B output output A=B output output A
DFPCOMP www.DataSheet4U.com Floating Point Comparator Unit ver 2.10 OVERVIEW DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ ◊ ◊ The DFPCOMP compares two arguments. The input numbers format is according to IE.

DFPCOMP Features

* Full IEEE-754 compliance Single precision real format support Simple interface No programming required 1 level pipeline Results available at every clock Fully configurable Fully synthesizable, static synchronous design with no internal tri-states Deli

DFPCOMP_DigitalCoreDesign.pdf

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Datasheet Details

Part number:

DFPCOMP

Manufacturer:

Digital Core Design

File Size:

170.88 KB

Description:

Floating point comparator unit.

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DFPCOMP DFPCOMP Floating Point Comparator Unit Digital Core Design

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