M12L128168A-6BVAG2S - 2M x 16 Bit x 4 Banks Synchronous DRAM
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst
M12L128168A-6BVAG2S Features
* JEDEC standard 3.3V power supply
* LVTTL compatible with multiplexed address
* Four banks operation
* MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave )
* All inputs are sampled at the p
