EDD1232AABH Datasheet (Elpida Memory)

EDD1232AABH, 128M bits DDR SDRAM

The EDD1232AABH is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks.

Read and write operations are performed at the cross points of the CK and the /CK.

This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.

Data strobe (DQS) both for read and w

EDD1232AABH Features

* Power supply: VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V

* Data rate: 333Mbps/266Mbps (max.)

* Double Data Rate architecture; two data transfers per clock cycle

* Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the r