EDD1232ABBH Datasheet - Elpida Memory

128M bits DDR SDRAM

* ×32 organization

* Double-data-rate architecture; two data transfers per clock cycle

* The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture

* Bi-directional data strobe (DQS) is trans

EDD1232ABBH

Elpida Memory

515.23 KB

128m bits ddr sdram.
DATA SHEET 128M bits DDR SDRAM EDD1232ABBH (4M words × 32 bits) Specifications Density: 128M bits Organization ⎯ 1M words × 32 .

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EDD1232ABBH 128M bits DDR SDRAM Elpida Memory

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