EM638325 Datasheet - Etron Technology

EM638325 2M x 32 Synchronous DRAM

Table 3. Pin Details of EM638325 SDRAM Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE acti.

EM638325 Features

* Fast access time: 5.5/5.5 ns

* Fast Clock rate: 166/143 MHz

* Fully synchronous operation

* Internal pipelined architecture

* Four internal banks (512K x 32bit x 4bank)

* Programmable Mode - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full pag

EM638325_EtronTechnology.pdf