EP520 Datasheet - Eureka

EP520 SDRAM Controller

The EP520 SDRAM controller interfaces between a processor or DMA device with an SDRAM. It performs SDRAM read and write access based on processor or DMA requests. SDRAM timing such as row and column latency, precharge timing, and row access length are automatically handled by the SDRAM controller. A.

EP520 Features

* None Provided with Core Documentation User guide Design File Formats EDIF netlist Constraints File Top520.ucf Verification VHDL or Verilog test bench Instantiation Templates VHDL, Verilog Reference designs & None application notes Additional Items None Simulation Tool Used Model Technology Modelsim™

EP520_Eureka.pdf