EP520 - SDRAM Controller

Datasheet Details

The EP520 SDRAM controller interfaces between a processor or DMA device with an SDRAM.

None Provided with Core Documentation User guide Design File Formats EDIF netlist Constraints File Top520.ucf Verification VHDL or Verilog test bench Instantiation Templates VHDL, Verilog Reference designs & None.

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Published: Mar 13, 2007 |