Description
Symbol
Description
SA[21:0] D[35:0]
Q[35:0] QVLD[1:0]
CK, CK KD[1:0], KD[1:0]
CQ[1:0], CQ[1:0]
R W MRW
PLL
RST ZQ ZT RCS
Address
Read address is registered on CK and write address is registered on CK.
Registered on KD and KD during Write operations.
Aligned with CQ and CQ during Read operations.
Driven high one half cycle b
Features
- 4Mb x 36 and 8Mb x 18 organizations available.
- Organized as 16 logical memory banks.
- 1333 MHz maximum operating frequency.
- 2.666 BT/s peak transaction rate (in billions per second).
- 192 Gb/s peak data bandwidth (in x36 devices).
- Separate I/O DDR Data Buses.
- Non-multiplexed DDR Address Bus.
- Two operations - Read and Write - per clock cycle.
- Certain address/bank restrictions on Read and Write ops.
- Burst of 2.