250 MHz *357 MHz 1.8 V VDD 1.5 V or 1.8 V HSTL I/O Because GS8150V18/36A are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock.
Write cycles are internally selftimed and initiated by the rising edge of the clock input.
GS8150V36AB-357 Features
* Register-Register Late Write mode, Pipelined Read mode
* 1.8 V +150/
* 100 mV core power supply
* 1.5 V or 1.8 V HSTL Interface
* ZQ controlled programmable output drivers
* Dual Cycle Deselect
* Fully coherent read and write pipelines
GS8150V18AB-357_GSITechnology.pdf
Datasheet Details
GS8150V36AB-357, GS8150V18AB-357
GSI Technology
842.40 KB
1m x 18/ 512k x 36 18mb register-register late write sram.
This datasheet PDF includes multiple part numbers: GS8150V36AB-357, GS8150V18AB-357.
Please refer to the document for exact specifications by model.
📁 Related Datasheet
📌 All Tags
