Datasheet4U Logo Datasheet4U.com

HD74LV273A - Octal D-type Flip-Flops with Clear

Datasheet Summary

Description

The HD74LV273A has eight edge trigger D-type flip-flops with clear in a 20-pin package.

Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input.

The clear input when low, sets all outputs to a low state.

Features

  • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max. ) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max. ) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V) Function Table Inputs CLR L H H H CLK X ↑ ↑ ↓ D X H L X Output Q L H L Q0 Note: H: High level L: Low level X: Immateri.

📥 Download Datasheet

Datasheet preview – HD74LV273A

Datasheet Details

Part number HD74LV273A
Manufacturer Hitachi Semiconductor
File Size 65.79 KB
Description Octal D-type Flip-Flops with Clear
Datasheet download datasheet HD74LV273A Datasheet
Additional preview pages of the HD74LV273A datasheet.

📁 Similar Datasheet

  • HD74LV273A - Octal D-type Flip-Flops (Renesas)
  • HD74LV27A - Triple 3-input Positive NOR Gates (Renesas)
  • HD74LV20A - Dual 4-input Positive NAND Gates (Renesas)
  • HD74LV21A - Dual 4-input Positive AND Gates (Renesas)
  • HD74LV221A - Dual Monostable Multivibrators (Renesas)
  • HD74LV240A - Octal Buffers / Drivers (Renesas)
  • HD74LV244A - Octal Buffers / Drivers (Renesas)
  • HD74LV245A - Octal Bus Transceivers (Renesas)
  • HD74LV2G00A - Dual 2-input NAND Gates (Renesas Technology)
  • HD74LV2G02A - Dual 2-input NOR Gates (Renesas Technology)
Other Datasheets by Hitachi Semiconductor

Full PDF Text Transcription

Click to expand full text
HD74LV273A Octal D-type Flip-Flops with Clear ADE-205-273 (Z) 1st Edition April 1999 Description The HD74LV273A has eight edge trigger D-type flip-flops with clear in a 20-pin package. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. Low-voltage and high-speed operation is suitable for battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.
Published: |