HY5DU56422BT-D4 - (HY5DU56x22BT-D4x) 256M-P DDR SDRAM

Hynix Semiconductor

Datasheet Details

Part number	HY5DU56422BT-D4
Manufacturer	Hynix Semiconductor
File Size	250.38 KB
Description	(HY5DU56x22BT-D4x) 256M-P DDR SDRAM
Datasheet	HY5DU56422BT-D4_HynixSemiconductor.pdf

and is subject to change without notice.

VDD/VDDQ = 2.5 ~ 2.7V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align D.

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Published: Dec 8, 2006 |